This invention relates to a pulse-width modulated (pwm) controller, and particularly for such a controller when used to control a switched-mode power supply.
Switched-Mode Power Supplies (SMPS) are being increasingly used in many domestic and industrial applications. In applications such as television or computer monitor, the application may require a number of states or modes. of operation. A first xe2x80x98offxe2x80x99 mode occurs when there is no power supplied to a device (or when a master switch is off); a second xe2x80x98onxe2x80x99 mode occurs when the device is switched on an operating normally; and a third mode (referred to as a standby mode) occurs when the device is to remain powered, but with reduced functions and reduced power consumption. A standby mode may be encountered in a television via an xe2x80x98offxe2x80x99 switch of a remote control, which typically does not switch the television fully off, but allows certain circuitry within the television to remain powered, so that if the xe2x80x98onxe2x80x99 button of the remote control is pressed, the television will return to the xe2x80x98onxe2x80x99 mode.
There is a need to reduce the power consumed by the SMPS during standby mode, so that use of mains electricity is reduced. At present there is a goal to reduce the power consumption to a value of the order of 1 Watt.
Burst mode SMPS are known, which have an efficient power consumption in standby mode. However, there is a problem with SMPS operating in a burst mode which is that the periodicity of the bursts (or the frequency of bursting) will typically lie within the audible frequency range. This tends to generate audible noise for reasons which are not well understood and are certainly not predictable in advance of a finished prototype. Altering the frequency of bursting can help to reduce the noise as can altering the peak current generated by the SMPS during each burst (note this may be achieved if the frequency of burstingxe2x80x94or at any rate the duty rate of burstingxe2x80x94is increased without reducing the averaged power supplied to the microprocessor on the secondary side of the SMPS). Typically, however, there is no way to alter the frequency of bursting meaning that designers must simply hope that the finished product is not too noisy in standby mode.
This invention seeks to provide a PWM controller which mitigates the above mentioned disadvantages.
According to the present invention there is provided a PWM controller according to claim 1.
The advantage of such a controller having a third phase of operation (which may also be referred to as a latched-off phase) is that the duty cycle and the frequency of bursting during a standby-mode of operation may be greatly reduced without having to especially adapt the rate at which the start-up current source provides current to the Vcc node during the first phase (often referred to as a start-up phase), because the latched-off phase can be made relatively long compared to either of the other phases (when in standby mode).
Preferably, the pwm controller includes a third mode duration controller for controlling the duration of the third mode. The advantage of this is that the frequency of bursting may be varied to accommodate different circumstances. For example, there are two major reasons that the pwm controller could enter into a bursting mode of operation. The first is when there is a fault condition such as the secondary side demanding too much power (i.e. more than the SMPS is designed to deliver) probably as a result of a short circuit in the device being supplied by the secondary side. In this situation, it is desirable that the bursting frequency should be as low as possible, and since this condition represents an undesired state of affairs, there is no harm in any audible noise generated by the SMPS since it is desirable that this fault should be corrected rather than tolerated. The second reason for the pwm controller to enter a bursting mode of operation is when the SMPS is in a standby mode. In this mode, the most important consideration is the amount of audible noise which is generated by the SMPS as a whole as a result of any mechanical resonance in the transformer or other parts of the SMPS. Having a third mode duration controller which is able to vary the bursting frequency during standby mode compared to a fault condition, permits a standby bursting frequency to be used which will cause the least possible audible noise.
Preferably, the pwm controller includes a Vcc detector connected to the Vcc node for detecting the voltage at the Vcc node, wherein the third phase is commenced when the detected voltage at the Vcc node falls below a first under voltage level and is ended when the detected voltage at the Vcc node falls below a second under voltage level. This provides a very simple way to determine when the pwm controller should be in a third or latched-off phase.
Preferably, the third phase duration controller includes a third phase current controller for controlling the amount of current drawn by the pwm controller from the Vcc node during the third phase. Preferably, the third phase current controller includes a programming node to which an external programming resistor may be connected (between the programming node and ground), such that the rate at which current drawn by the pwm controller from the Vcc node may be set by choosing an appropriate programming resistor (the rate will vary in an inverse dependence to the value of the programming resistor). This provides a particularly convenient way for a designer using the pwm controller to alter the frequency of bursting during standby mode to minimize audible noise, since resistors are cheap and there are many different magnitudes of resistance available (corresponding to many different frequencies of bursting).
Preferably, the pwm controller further includes a switch which is switchable between a first position in which the programming node is connected to a first voltage source which is ultimately powered from the Vcc node and a second position in which the programming node is isolated or is connected to a second voltage source which is ultimately powered from the Vcc node but which causes less current to be drawn from the Vcc node, for a given programming resistor, than when the switch is in its first position. In this way, the frequency of bursting may be varied between a first frequency when in standby mode (when the switch is in its first position) and a second (usually lower) frequency when in a fault mode.